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Enhanced
Features
s
Memory Systems Inc.
DM2203/2213 Multibank EDO EDRAM 512Kb x 8 Enhanced Dynamic RAM
Product Specification
8Kbit SRAM Cache Memory for 12ns Random Reads Within Four Active Pages (Multibank Cache) s Fast 4Mbit DRAM Array for 30ns Access to Any New Page s Write Posting Register for 12ns Random Writes and Burst Writes Within a Page (Hit or Miss) s 5ns Output Enable Access Time Allows Fast Interleaving s 256-byte Wide DRAM to SRAM Bus for 14.2 Gigabytes/Sec Cache Fill s On-chip Cache Hit/Miss Comparators Maintain Cache Coherency Without the Need for External Cache Control s A Hit Pin Outputs Status of On-chip Page Hit/Miss Comparators to Simplify Control
Output Latch Enable Allows Extended Data Output (EDO) For Faster System Operation s Hidden Precharge Cycles s Hidden Refresh Cycles s Write-per-bit Option (DM2213) for Parity and Video Applications s Extended 64ms Refresh Period for Low Standby Power s Standard CMOS/TTL Compatible I/O Levels and +5 Volt Supply s Low Profile 300-Mil 44-Pin TSOP-II Package s Industrial Temperature Range Option
s
Description
The Enhanced Memory Systems 4Mb EDRAM combines raw speed with innovative architecture to offer the optimum costperformance solution for high performance local or main memory in computer and embedded control systems. In most high speed applications, zero-wait-state operation can be achieved without secondary SRAM cache for system clock speeds of up to 83MHz without interleaving or 132MHz with two-way interleaving. The EDRAM outperforms conventional SRAM cache plus DRAM or synchronous DRAM memory systems by minimizing wait states on initial reads (hit or miss) and by eliminating writeback delays. Architectural similarity with JEDEC DRAMs allows a single memory controller design to support either slow JEDEC DRAMs or high speed EDRAMs. A system designed in this manner can provide a simple upgrade path to higher system performance. The 512K x 8 EDRAM has the same control and address interface as Enhanced's 4M x 1 and 1M x 4 EDRAM products so that EDRAMs of different organizations can be supported with the same controller design. The 512K x 8 EDRAM implements the following additional features which can be supported on new designs: s A controllable output latch provides an extended data out (EDO) mode. s Cache size is increased from 2Kbits to 8Kbits. The 8Kbit cache is organized as four 256 x 8 direct mapped row registers. s A hit pin is provided to tell the memory controller when a hit occurs to one of the on-chip cache row registers.
Architecture
The EDRAM architecture has a simple integrated SRAM cache which allows it to operate much like a page mode or static column DRAM.
Functional Diagram
/CAL Column Address Latch /HIT A 0 - A7 Column Decoder
Pin Configuration
VCC /F VSS DQ 0 VCC DQ 1 DQ 2 VSS DQ 3 QLE VCC /G DQ 4 VSS DQ 5 DQ 6 VCC DQ 7 VSS NC NC VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 VSS W/R /S A 10 A9 A8 A7 A6 A5 A4 VSS /RE /CAL VCC A3 A2 A1 A0 /WE NC /HIT VSS
4 - 9 Bit Comparators
4 - 256 X 8 Cache Pages (Row Registers)
QLE Sense Amps & Column Write Select /G I/O Control and Data Latches Row Decoder Memory Array (2048 X 256 X 8)
A0 - A10
4 - Last Row Read Address Latches
DQ 0 - DQ 7
/S /WE
Row Address Latch
/F W/R /RE
Row Adress and Refresh Control
A 0 - A9 Refresh Counter
VCC VSS
The information contained herein is subject to change without notice. Enhanced reserves the right to change or discontinue this product without notice.
(c) 1996 Enhanced Memory Systems Inc. 1850 Ramtron Drive, Colorado Springs, CO Telephone (800) 545-DRAM; Fax (719) 488-9095; http://www.csn.net/ramtron/enhanced
80921 38-2105-001
The EDRAM's SRAM cache is integrated into the DRAM array as tightly coupled row registers. The 512K x 8 EDRAM has a total of four independent DRAM memory banks each with its own 256 x 8 SRAM row register. Memory reads always occur from the cache row register of one of these banks as specified by row address bits A8 and A9 (bank select). When the internal comparator detects that the row address matches the last row read from any of the four DRAM banks (page hit), the SRAM is accessed and data is available on the output pins in 12ns from column address input. The /HIT pin is driven low during a page hit to signify to the DRAM control logic that data is available early. Subsequent reads within the page (burst reads or random reads) can continue at 12ns cycle time. When the row address does not match the last row read from any of the four DRAM banks (page miss), the new DRAM row is accessed and loaded into the appropriate SRAM row register and data is available on the output pins all within 30ns from row enable. In this case, the /HIT pin is driven high to signify to the control logic that data is available later. Subsequent reads within the page (burst reads or random reads) can continue at 12ns cycle time. During either read hit or read miss operations, a user controllable on-chip output data latch can be used to extend data output time to allow use of the full 83Mbyte/second bandwidth.
Since reads occur from the SRAM cache, the DRAM precharge can occur during burst reads. This eliminates the precharge time delay suffered by other DRAMs and SDRAMs when accessing a new page. The EDRAM has an independent on-chip refresh counter and dedicated refresh control pin to allow the DRAM array to be refreshed concurrently with cache read operations (hidden refresh). During EDRAM read accesses, data can be accessed in either static column or page mode depending upon the operation of the /CAL input. If /CAL is held high, new data is accessed with each new column address (static column mode). If /CAL is brought low during a read access, the column address is latched and new data will not be accessed until both the column address is changed and /CAL is brought high (page mode). A dedicated output enable (/G) with 5ns access time allows high speed two-way interleave without an external multiplexer. Memory writes are posted to the input data latch and directed to the DRAM array. During a write hit, the on-chip address comparator activates a parallel write path to the SRAM cache to maintain coherency. Random or page mode writes can be posted 5ns after column address and data are available. The EDRAM allows 12ns page mode cycle time for both write hits and write misses. Memory writes do not affect the contents of the cache row
Four Bank Cache Architecture
HIT0 HIT1 HIT2 HIT3 Bank 3 Bank 2 Bank 1 Bank 0 /HIT
Row Address Latch
Last Row Read Address Latch + 9-Bit Compare
RA0-10
Column Address Latch
CA0-7
1M Array
1M Array
1M Array
1M Array
D0-7
A0-10
Data-In Latch 256 x 8 Cache
Bank 0
CA0-7
256 x 8 Cache
Bank 1
256 x 8 Cache
Bank 2
256 x 8 Cache
Bank 3
(0,0) RA8, RA9
(0,1)
(1,0)
(1,1)
1 of 4 Selector
CAL QLE
Data-Out Latch
G S
Q0-7
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register except during a cache hit. Since the DRAM array can be written to at SRAM speeds, there is no need for complex writeback schemes. By integrating the SRAM cache as row registers in the DRAM array and keeping the on-chip control simple, the EDRAM is able to provide superior performance over standard slow 4Mb DRAMs. By eliminating the need for SRAMs and cache controllers, system cost, board space, and power can all be reduced.
DRAM Read Miss A DRAM read request is initiated by clocking /RE with W/R low and /F high. The EDRAM will compare the new row address to the LRR address latch for the bank specified by row address bits A8-9 (LRR: a 9-bit row address latch for each internal DRAM bank which is reloaded on each /RE active read miss cycle). If the row address does not match the LRR, the requested data is not in SRAM cache and a new row is fetched from the DRAM. The EDRAM will load the new row data into the SRAM cache and update the LRR latch. The data at the specified column address is available at the output pins at the greater of times tRAC, tAC, and tGQV. The /HIT output is driven high at time tHV after /RE to indicate the longer EDRAM Basic Operating Modes access time to the external control logic. /RE may be brought high The EDRAM operating modes are specified in the table below. after time t since the new row data is safely latched into SRAM RE cache. This allows the EDRAM to precharge the DRAM array while Hit and Miss Terminology In this datasheet, "hit" and "miss" always refer to a hit or miss data is accessed from SRAM cache. Additional locations within the currently active page may be accessed by providing new column to any of the four pages of data contained in the SRAM cache row addresses to the multiplex address inputs. New data is available at registers. There are four cache row registers, one for each of the the output at time tAC after each column address change in static four banks of DRAM. These registers are specified by the bank column mode. During any read cycle, it is possible to operate in select row address bits A8 and A9. The contents of these cache row registers is always equal to the last row that was read from each of either static column mode with /CAL=high or page mode with /CAL clocked to latch the column address. In page mode, data valid time the four internal DRAM banks (as modified by any write hit data). is determined by either t and t . AC CQV DRAM Read Hit DRAM Write Hit A DRAM read request is initiated by clocking /RE with W/R low A DRAM write request is initiated by clocking /RE while W/R, and /F high. The EDRAM will compare the new row address to the /CAL, /WE, and /F are high. The EDRAM will compare the new row last row read address latch for the bank specified by row address address to the LRR address latch for the bank specified by row bits A8-9 (LRR: a 9-bit row address latch for each internal DRAM address bits A8-9 (LRR: a 9-bit row address latch for each internal bank which is reloaded on each /RE active read miss cycle). If the DRAM bank which is reloaded on each /RE active read miss cycle). row address matches the LRR, the requested data is already in the If the row address matches the LRR, the EDRAM will write data to SRAM cache and no DRAM memory reference is initiated. The data both the DRAM page in the appropriate bank and its corresponding specified by the row and column address is available at the output SRAM cache simultaneously to maintain coherency. The write pins at the greater of times tAC or tGQV. The /HIT output is driven address and data are posted to the DRAM as soon as the column low at time tHV after /RE to indicate the shorter access time to the address is latched by bringing /CAL low and the write data is latched external control logic. Since no DRAM activity is initiated, /RE can by bringing /WE low (both /CAL and /WE must be high when
The EDRAM is designed to provide optimum memory performance with high speed microprocessors. As a result, it is possible to perform simultaneous operations to the DRAM and SRAM cache sections of the EDRAM. This feature allows the EDRAM to hide precharge and refresh operation during reads and maximize hit rate by maintaining page cache contents during write operations even if data is written to another memory page. These capabilities, in conjunction with the faster basic DRAM and cache speeds of the EDRAM, minimize processor wait states.
Functional Description
be brought high after time tRE1, and a shorter precharge time, tRP1, is required. Additional locations within the currently active page may be accessed concurrently with precharge by providing new column addresses to the multiplex address inputs. New data is available at the output at time tAC after each column address change in static column mode. During any read cycle, it is possible to operate in either static column mode with /CAL=high or page mode with /CAL clocked to latch the column address. In page mode, data valid time is determined by either tAC and tCQV.
EDRAM Basic Operating Modes
Function
Read Hit Read Miss Write Hit Write Miss Internal Refresh Low Power Standby Unallowed Mode
/S
L L L L X H H
/RE
H L
W/R
L L H H X X X
/F
H H H H L X H
A0-10
Row = LRR Row LRR Row = LRR Row LRR X X X 1mA Standby Current
Comment
No DRAM Reference, Data in Cache DRAM Row to Cache Write to DRAM and Cache, Reads Enabled Write to DRAM, Cache Not Updated, Reads Disabled
H = High; L = Low; X = Don't Care; O = High-to-Low Transition; LRR = Last Row Read
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initiating the write cycle with the falling edge of /RE). The write address and data can be latched very quickly after the fall of /RE (tRAH + tASC for the column address and tDS for the data). During a write burst sequence, the second write data can be posted at time tRSW after /RE. Subsequent writes within a page can occur with write cycle time tPC. With /G enabled and /WE disabled, read operations may be performed while /RE is activated in write hit mode. This allows read-modify-write, write-verify, or random read-write sequences within the page with 12ns cycle times. During a write hit sequence, the /HIT output is driven low. At the end of any write sequence (after /CAL and /WE are brought high and tRE is satisfied), /RE can be brought high to precharge the memory. Cache reads can be performed concurrently with precharge (see "/RE Inactive Operation"). When /RE is inactive, the cache reads will occur from the page accessed during the last /RE active read cycle. During write sequences, a write operation is not performed unless both /CAL and /WE are low. As a result, the /CAL input can be used as a byte write select in multi-chip systems. DRAM Write Miss A DRAM write request is initiated by clocking /RE while W/R, /CAL, /WE, and /F are high. The EDRAM will compare the new row address to the LRR address latch for the bank specified for row address bits A8-9 (LRR: a 9-bit row address latch for each internal DRAM bank which is reloaded on each /RE active read miss cycle). If the row address does not match any of the LRRs, the EDRAM will write data to the DRAM page in the appropriate bank and the contents of the current cache is not modified. The write address and data are posted to the DRAM as soon as the column address is latched by bringing /CAL low and the write data is latched by bringing /WE low (both /CAL and /WE must be high when initiating the write cycle with the falling edge of /RE). The write address and data can be latched very quickly after the fall of /RE (tRAH + tASC for the column address and tDS for the data). During a write burst sequence, the second write data can be posted at time tRSW after /RE. Subsequent writes within a page can occur with write cycle time tPC. During a write miss sequence, the /HIT output is driven high, cache reads are inhibited, and the output buffers are disabled (independently of /G) until time tWRR after /RE goes high. At the end of a write sequence (after /CAL and /WE are brought high and tRE is satisfied), /RE can be brought high to precharge the memory. Cache reads can be performed concurrently with the precharge (see "/RE Inactive Operation"). When /RE is inactive, the cache reads will occur from the page accessed during the last /RE active read cycle. During write sequences, a write operation is not performed unless both /CAL and /WE are low. As a result, /CAL can be used as a byte write select in multi-chip systems.
capable of fast hit/miss comparison. In this case, the controller can avoid the time required to perform row/column multiplexing on hit cycles.
Function
Cache Read (Static Column) Cache Read (Page Mode)
/S
L L
/G
L L
/CAL
H
A0-7
Col Adr Col Adr
EDO Mode and Output Latch Enable Operation The QLE and /CAL inputs can be used to create extended data output (EDO) mode timings in either static column or page modes. The 512K x 8 EDRAM has an output latch enable (QLE) that can be used to extend the data output valid time. The output latch enable operates as shown in the following table. When QLE is low, the latch is transparent and the EDRAM operates identically to the standard 4M x 1 and 1M x 4 EDRAMs. When /CAL is high during a static column mode read, the QLE input can be used to latch the output to extend the data output valid time. QLE can be held high during page mode reads. In this case, the data outputs are latched while /CAL is high and open when /CAL is not high.
QLE
L H
/CAL
X H Output Transparent
Comments
Output Latched When QLE=H (Static Column EDO) Output Latched When /CAL=H (Page Mode EDO)
When output data is latched and /S goes high, data does not go Hi-Z until /G is disabled or either QLE or /CAL goes low to unlatch data.
/RE Inactive Operation Data may be read from the SRAM cache without clocking /RE. This capability allows the EDRAM to perform cache read operations during precharge and refresh cycles to minimize wait states. It is only necessary to select /S and /G and provide the appropriate column address to read data as shown in the table below. In this mode of operation, the cache reads will occur from the page accessed during the last /RE active read cycle. To perform a cache read in static column mode, /CAL is held high, and the cache contents at the specified column address will be valid at time tAC after address is stable. To perform a cache read in page mode, /CAL is clocked to latch the column address. When /RE is inactive, the hit pin is not driven and is in a high impedance state. This option is desirable when the external control logic is
Write-Per-Bit Operation The DM2213 version of the 512Kb x 8 EDRAM offers a writeper-bit capability which allows single bits of the memory to be selectively written without altering other bits in the same word. This capability may be useful for implementing parity or masking data in video graphics applications. The bits to be written are determined by a bit mask data word which is placed on the I/O data pins DQ0-7 prior to clocking /RE. The logic one bits in the mask data select the bits to be written. As soon as the mask is latched by /RE, the mask data is removed and write data can be placed on the databus. The mask is only specified on the /RE transition. During page mode burst write operations, the same mask is used for all write operations. Internal Refresh If /F is active (low) on the assertion of /RE, an internal refresh cycle is executed. This cycle refreshes the row address supplied by an internal refresh counter. This counter is incremented at the end of the cycle in preparation for the next /F refresh cycle. At least 1,024 /F cycles must be executed every 64ms. /F refresh cycles can be hidden because cache memory can be read under column address control throughout the entire /F cycle. /F cycles are the only active cycles where /S can be disabled. /CAL Before /RE Refresh ("/CAS Before /RAS") /CAL before /RE refresh, a special case of internal refresh, is discussed in the "Reduced Pin Count Operation" section.
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/RE Only Refresh Operation Although /F refresh using the internal refresh counter is the recommended method of EDRAM refresh, an /RE only refresh may be performed using an externally supplied row address. /RE refresh is performed by executing a write cycle (W/R, /G, and /F are high) where /CAL is not clocked. This is necessary so that the current cache contents and LRR are not modified by the refresh operation. All combinations of addresses A0-9 must be sequenced every 64ms refresh period. A10 does not need to be cycled. Read refresh cycles are not allowed because a DRAM refresh cycle does not occur when a read refresh address matches the LRR address latch. Low Power Mode The EDRAM enters its low power mode when /S is high. In this mode, the internal DRAM circuitry is powered down to reduce standby current to 1mA. Initialization Cycles A minimum of eight /RE active initialization cycles (read, write, or refresh) are required before normal operation is guaranteed. Following these start-up cycles, two read cycles to different row addresses must be performed for each of the four internal banks of DRAM to initialize the internal cache logic. Row address bits A8 and A9 define the four internal DRAM banks. Unallowed Mode Read, write, or /RE only refresh operations must not be performed to unselected memory banks by clocking /RE when /S is high. Reduced Pin Count Operation Although it is desirable to use all EDRAM control pins to optimize system performance, the interface to the EDRAM may be simplified to reduce the number of control lines by either tying pins to ground or by tying one or more control inputs together. The /S input can be tied to ground if the low power standby mode is not required. The QLE input can be tied low if output latching is not required, or it can be tied high if "extended data out" (hyper page mode) is required. The /HIT output pin is not necessary for device operation. The /CAL and /F pins can be tied together if hidden refresh operation is not required. In this case, a CBR refresh (/CAL before /RE) can be performed by holding the combined input low prior to /RE. A CBR refresh does not require that a row address be supplied when /RE is asserted. The timing is identical to /F refresh cycle timing. The /WE input can be tied to /CAL if independent posting of column addresses and data are not required during write operations. In this case, both column address and write data will be latched by the combined input during writes. The W/R and /G inputs can be tied together if reads are not required during a write hit cycle. If these techniques are used, the EDRAM will require only three control lines for operation (/RE, /CAS [combined /CAL, /F, and /WE], and W/R [combined W/R and /G]). The simplified control interface still allows the fast page read/write cycle times, fast random read/ write times, and hidden precharge functions available with the EDRAM.
operations, /RE can be brought high as soon as data is loaded into cache to allow early precharge.
Pin Descriptions
/RE -- Row Enable This input is used to initiate DRAM read and write operations and latch a row address. It is not necessary to clock /RE to read data from the most currently read SRAM row register. On read
/CAL -- Column Address Latch This input is used to latch the column address and in combination with /WE to trigger write operations. When /CAL is high, the column address latch is transparent. When /CAL transitions low, it latches the address present while /CAL was high. /CAL can be toggled when /RE is low or high. However, /CAL must be high during the high-to-low transition of /RE except for /F refresh cycles. If QLE is high during a read, /CAL will hold data output until it transitions low. W/R -- Write/Read This input along with /F specifies the type of DRAM operation initiated on the low going edge of /RE. When /F is high, W/R specifies either a write (logic high) or read operation (logic low). /F -- Refresh This input will initiate a DRAM refresh operation using the internal refresh counter as an address source when /F is low on the low going edge of /RE. /WE -- Write Enable This input controls the latching of write data on the input data pins. A write operation is initiated when both /CAL and /WE are low. /G -- Output Enable This input controls the gating of read data to the output data pins during read operations. /S -- Chip Select This input is used to power up the I/O and clock circuitry. When /S is high, the EDRAM remains in its low power mode. /S must remain active throughout any read or write operation. With the exception of /F refresh cycles, /RE should never be clocked when /S is inactive. DQ0-7 -- Data Input/Output These bidirectional data pins are used to read and write data to the EDRAM. On the DM2213 write-per-bit memory, these pins are also used to specify the bit mask used during write operations. A0-10 -- Multiplex Address These inputs are used to specify the row and column addresses of the EDRAM data. The 11-bit row address is latched on the falling edge of /RE. The 8-bit column address can be specified at any other time to select read data from the SRAM cache or to specify the write column address during write cycles. QLE -- Output Latch Enable This input enables the output latch. When QLE is low, the output latch is transparent. Data is latched when both /CAL and QLE are high. This allows output data to be extended during either static column or page mode read cycles. /HIT -- Hit Pin This output pin will be driven during /RE active read or write cycles to indicate the hit/miss status of the cycle. VCC Power Supply These inputs are connected to the +5 volt power supply. VSS Ground These inputs are connected to the power supply ground connection.
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Pin Names
Pin Names
A0-10 /RE DQ0-7 /CAL W/R VCC VSS Address Inputs Row Enable Data In/Data Out Column Address Latch Write/Read Control Power (+5V) Ground
Function
Pin Names
/WE /G /F /S /HIT QLE NC Write Enable Output Enable Refresh Control Chip Select Hit Output
Function
Output Latch Enable Not Connected
Absolute Maximum Ratings
(Beyond Which Permanent Damage Could Result)
Capacitance
Ratings
- 1 ~ VCC+1 - 1 ~ VCC+1 - 1 ~ 7v -40 ~ +85C -55 ~ 150C Class 1 50mA*
Description
Input Voltage (VIN) Output Voltage (VOUT) Power Supply Voltage (VCC) Ambient Operating Temperature (TA) Storage Temperature (TS) Static Discharge Voltage (Per MIL-STD-883 Method 3015) Short Circuit O/P Current (IOUT)
*One output at a time; short duration.
Description
Input Capacitance Input Capacitance Input Capacitance Output Capacitance I/O Capacitance
Max
5pf 6pf 2pf 4pf 6pf A0-10
Pins
/RE, /CAL, W/R, /WE, /F, /S, QLE /G /HIT DQ0-7
AC Test Load and Waveforms
VIN Timing Reference Point at VIL and VIH VOUT Timing Referenced to 1.5 Volts
5.0V R1 = 828 Output GND VIL VIL VIH VIH
R2 = 295
CL = 50pf
5ns
5ns
Load Circuit
Input Waveforms
2-40
Electrical Characteristics
TA = 0 to 70C (Commercial), -40 to 85C (Industrial)
Symbol
VCC VIH VIL VOH VOL Vi(L) V0(L)
Parameters
Supply Voltage Input High Voltage Input Low Voltage Output High Level Output Low Level Input Leakage Current Output Leakage Current
Min
4.75V 2.4V -1.0V 2.4V
Max
5.25V VCC+1 0.8V IOUT = - 5mA 0.4V IOUT = 4.2mA
Test Conditions
All Voltages Referenced to VSS
-10A -10A
10A 10A
0V VIN 6.5V, All Other Pins Not Under Test = 0V 0V VIN, 0V VOUT 5.5V
Symbol
ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 ICCT
Operating Current
Random Read Fast Page Mode Read Static Column Read Random Write Fast Page Mode Write Standby Average Typical Operating Current
33MHz Typ(1)
110mA 65mA 55mA 135mA 50mA 1mA 30mA
-12 Max
225mA 145mA 110mA 190mA 135mA 1mA --
-15 Max
180mA 115mA 90mA 150mA 105mA 1mA --
Test Condition
/RE, /CAL, /G and Addresses Cycling: tC = tC Minimum /CAL, /G and Addresses Cycling: tPC = tPC Minimum /G and Addresses Cycling: tAC = tAC Minimum /RE, /CAL, /WE and Addresses Cycling: tC = tC Minimum /CAL, /WE and Addresses Cycling: tPC = tPC Minimum All Control Inputs Stable VCC - 0.2V, Outputs Driven See "Estimating EDRAM Operating Power" Application Note
Notes
2, 3 2, 4 2, 4 2, 3 2, 4
1
(1) "33MHz Typ" refers to worst case ICC expected in a system operating with a 33MHz memory bus. See power applications note for further details. This parameter is not 100% tested or guaranteed. (2) ICC is dependent on cycle rates and is measured with CMOS levels and the outputs open. (3) ICC is measured with a maximum of one address change while /RE = VIL (4) ICC is measured with a maximum of one address change while /CAL = VIH
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Switching Characteristics
Symbol
tAC(1) tACH tACI tAHQ tAQH tAQX tASC tASR tC tC1 tCAE tCAH tCH tCHR tCHW tCLV tCQH tCQV tCQX tCRP tCWL tDH tDMH tDMS tDS tGQV(1) tGQX(2,3) tGQZ(4,5) tHV tHZ tMH tMSU tNRH tNRS tPC tQCI tQH Column Address Access Time Column Address Valid to /CAL Inactive (Write Cycle) Address Valid to /CAL Inactive (QLE High) Column Address Hold From QLE High (/CAL=H) Address Valid to QLE High Column Address Change to Output Data Invalid Column Address Setup Time Row Address Setup Time Row Enable Cycle Time
VCC = 5V 5%, TA = 0 to 70C, (Commercial) -40 to 85C, (Industrial) CL = 50pf
-12 Description Min Max
12 12 12 0 12 5 5 5 55 20 5 0 5 -2 0 7 5 15 5 5 5 0 1 5 5 5 0 0 5 5 5 0 0 5 0 5 12 0 5 0 0 5 0 5 15 0 5 0 0 5 5 5 0 1.5 5 5 5 15 15 0 15 5 5 5 65 25 6 0 5 -2 0
-15 Min Max
15
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Row Enable Cycle Time, Cache Hit (Row=LRR), Read Cycle Only Column Address Latch Active Time Column Address Hold Time Column Address Latch High Time (Latch Transparent) /CAL Inactive Lead Time to /RE Inactive (Write Cycles Only) Column Address Latch High to Write Enable Low (Multiple Writes) Column Address Latch Low to Data Valid (QLE High) Column Address Latch Low to Data Invalid (QLE High) Column Address Latch High to Data Valid Column Address Latch Inactive to Data Invalid Column Address Latch Setup Time to Row Enable /WE Low to /CAL Inactive Data Input Hold Time Mask Hold Time From Row Enable (Write-Per-Bit) Mask Setup Time to Row Enable (Write-Per-Bit) Data Input Setup Time Output Enable Access Time Output Enable to Output Drive Time Output Turn-Off Delay From Output Disabled (/G) Hit Valid From Row Enable Hit Turn-Off From Row Enable Going High /F and W/R Mode Select Hold Time /F and W/R Mode Select Setup Time /CAL, /G, and /WE Hold Time For /RE-Only Refresh /CAL, /G, and /WE Setup Time For /RE-Only Refresh Column Address Latch Cycle Time QLE High to /CAL Inactive QLE High Time
7
ns ns
15
ns ns ns ns ns ns ns ns
5 5 5 5
ns ns ns ns ns ns ns ns ns ns ns ns
2-42
Switching Characteristics (continued)
Symbol
tQL tQQH tQQV tRAC(1) tRAC1 tRAH tRE tRE1 tREF tRGX tRQX1 tRP tRP1 tRRH tRSH tRSW tRWL tSC tSHR tSQV(1) tSQX(2,3) tSQZ
(4,5) (1)
VCC = 5V 5%, TA = 0 to 70C(Commercial), -40 to 85C (Industrial), CL = 50pf
Description
QLE Low Time Data Hold From QLE Inactive Data Valid From QLE Low Row Enable Access Time, On a Cache Miss Row Enable Access Time, On a Cache Hit (Limit Becomes tAC) Row Address Hold Time Row Enable Active Time Row Enable Active Time, Cache Hit (Row=LRR) Read Cycle Refresh Period Output Enable Don't Care From Row Enable (Write, Cache Miss), DQ = Hi-Z
-12 Min
5 2 7.5 30 15 1 30 8 64 9 0 20 8 0 12 35 12 12 0 12 0 0 5 1 12 5 0 5 5 12 0 0 5 12 12 12 0 0 5 10 12 8 0 0 5 1 15 5 0 5 5 12 25 10 0 15 40 15 15 0 10 100000 1.5 35 10
-15 Max Min
5 2 7.5 35 17
Max
Units
ns ns ns ns ns ns
100000
ns ns
64
ms ns
(2,5)
Row Enable High to Output Turn-On After Write Miss Row Precharge Time Row Precharge Time, Cache Hit (Row=LRR) Read Cycle Write Enable Don't Care From Row Enable (Write Only) Last Write Address Latch to End of Write Row Enable to Column Address Latch Low For Second Write Last Write Enable to End of Write Column Address Cycle Time Select Hold From Row Enable Chip Select Access Time Output Turn-On From Select Low Output Turn-Off From Chip Select Select Setup Time to Row Enable Transition Time (Rise and Fall) Write Enable Cycle Time Column Address Latch Low to Write Enable Inactive Time Write Enable Hold After /RE Write Enable Inactive Time Write Enable Active Time
15
ns ns ns ns ns ns ns ns ns
15 15 10
ns ns ns ns
tSSR tT tWC tWCH tWHR(6) tWI tWP tWQV
(1)
10
ns ns ns ns ns ns
Data Valid From Write Enable High Data Output Turn-On From Write Enable High Data Turn-Off From Write Enable Low Write Enable Setup Time to Row Enable Write to Read Recovery (Following Write Miss)
15 15 15
ns ns ns ns
tWQX(2,5) tWQZ(3,4) tWRP tWRR
15
ns
(1) VOUT Timing Reference Point at 1.5V; (2) Parameter Defines Time When Output is Enabled (Sourcing or Sinking Current) and is Not Referenced to VOH or VOL; (3) Minimum Specification is Referenced from VIH and Maximum Specification is Referenced from VIL on Input Control Signal; (4) Parameter Defines Time When Output Achieves Open-Circuit Condition and is Not Referenced to VOH or VOL; (5) Minimum Specification is Referenced from VIL and Maximum Specification is Referenced from VIH on Input Control Signal; (6) On DM2213, tWHR Minimum is tDS
2-43
/RE Inactive Cache Read Hit (Static Column Mode)
/RE
/F
W/R
A0-7
A0-10
Column 1 t SC
Column 2 t SC
Column 3 t SC
Column 4
/CAL
/WE
t AC t AQX t AC t AQX Data 1 t GQV Data 2 t AC t AQX Data 3 Data 4 t GQZ t AC
DQ0-7
Open t GQX
/G
t SQX t SQV Open t SQZ
/S /HIT
Don't Care or Indeterminate NOTES: 1. Data accessed during /RE inactive read is from the row address specified during the last /RE active read cycle.
2-44
/RE Inactive Cache Read Hit (Page Mode)
/RE
/F
W/R
A0-7
t CAH Column 1 t ASC t CAH t CAE t PC Column 2 t ASC t CH Row
A0-10
/CAL
t CQV
/WE
t AC t CQX
DQ0-7
Open t AC t GQX
Data 1 t GQZ t GQV t SQX t SQV t SQZ
Data 2
/G
/S /HIT
Open Don't Care or Indeterminate NOTES: 1. Data accessed during /RE inactive read is from the row address specified during the last /RE active read cycle.
2-45
/RE Active Cache Read Hit (Static Column Mode)
/RE
t RE1 t MSU t MH
t C1
t RP1
/F
t MSU t MH
W/R
t ASR t RAH
A0-7
A0-10
Row t CRP
Column 1 t SC
Column 2 t SC
Column 3 t SC
Column 4
/CAL
/WE
t AC t RAC1 t AQX Data 1 t AC t AQX Data 2 t AC t AQX Data 3 Data 4 t GQZ t GQV t SHR t SSR t SQZ t HZ Open Don't Care or Indeterminate t AC
DQ0-7
Open t GQX
/G
/S
t HV
/HIT
Open
2-46
/RE Active Cache Read Hit (Page Mode)
/RE
t RE1 t MSU t MH
t C1 t RP1
/F
t MSU t MH
W/R
t ASR t RAH
A0-7
t CAH Column 1 Column 2 t CAH t CAE t PC t ASC t CH Row
A0-10
Row t CRP
t ASC
/CAL
t CQV
/WE
t RAC1 t AC t CQX Data 1 t AC t GQX t GQZ t GQV t SHR t SSR t SQZ t HZ Open Don't Care or Indeterminate Data 2
DQ0-7
Open
/G
/S
t HV
/HIT
Open
2-47
/RE Active Cache Read Miss (Static Column Mode)
/RE
t MSU t MH
t RE
tC t RP
/F
t MSU t MH
W/R
t ASR
A0-10
t RAH
A0-7
t SC Column 1
A0-7
A0-10
A0-10
Row t CRP
Column 2
Row
/CAL
t AQX
/WE
t AC t RAC t AQX Data 1 t GQX t GQV t GQZ t SHR t SSR t SQZ t HZ Open Don't Care or Indeterminate Data 2 t AC
DQ0-7
Open
/G
/S
t HV
/HIT
Open
2-48
/RE Active Cache Read Miss (Page Mode)
tC t RP t MH
/RE
t MSU
t RE
/F
t MSU t MH
W/R
t ASR
A0-10
t RAH
A0-7
A0-7
t CAH Column 2 t ASC t CAH t CAE t PC t CH Row
A0-10
A0-10
Row t CRP
Column 1 t ASC
/CAL
t CQV
/WE
t RAC t AC t CQX Data 1 t AC t GQZ Data 2
DQ0-7
Open
/G
t SSR t GQX t GQV t SHR t SQZ
/S
t HV t HZ Open Don't Care or Indeterminate
/HIT
Open
2-49
Output Latch Enable Operation (Static Column EDO Mode Read)
/CAL
t AC t AC Column 2 t AHQ Data 1 t AQH t QQV t QL t QH t QQH Data 2
A0-7
t AQX
Column 1
DQ 0-7
QLE
Output Latch Enable Operation (Page Mode EDO Read)
t PC t QCI t CAE t CLV t AC Column 2 t CQH Data 1 t CQV Data 2 t CH
/CAL
t ACI t AC
A 0-7
t AQX
Column 1
DQ 0-7
QLE
Output Latch Enable Operation (Asynchronous Access)
t PC t CAE t CH
/CAL
t QCI t ACI t ACI Column 2 t CQV t AC Data 1 t QQH t QQV t QQV t QL t QH t QQV Data 2 t ACI Column 3 t CQV t AC Data 3
A 0-7
Column 1 t AC
DQ 0-7
QLE
t QQH
2-50
Burst Write (Hit or Miss) Followed By /RE Inactive Cache Reads
t RE
/RE
t MSU t MH t RP
/F
t MSU t MH
W/R
t ASR t RAH t A0-7 RSW t ASC t CRP t CAH t ACH t CWL t CH t PC t CHW t WI t RWL t DH Data 2 t GQX t AC Cache (Column n) t CAH
A0-7 A0-7
A0-10
Row
A0-10
Column 1
Column 2 t ACH t RSH t CAE t WCH t WP t WC t DH t DS t CWL t CHR
Column n
/CAL
t WRP
t CAE t WCH
t WP t WHR
t RRH t WRR
/WE
t DS
DQ0-7
Open
Data 1
/G
t SSR t GQV
/S
t HV t HZ Open Don't Care or Indeterminate NOTES: 1. /G becomes a don't care after tRGX during a write miss.
/HIT
Open
2-51
Read/Write During Write Hit Cycle (Can Include Read-Modify-Write)
/RE
t MSU t MH
t RE
tC t RP
/F
t MSU t MH
W/R
t ASR t RAH
A0-7
t CAH Column 2 t ACH t CAE t WCH
t AC Column 3 t RSH t CHR t CQV t RRH
A0-10
t CRP
Row
Column 1
t ASC
/CAL
t WRP
/WE
t AC
t WHR
t WP t AQX t DS
t CWL t RWL
t WQV Read Data t GQZ t WQX t GQV
DQ0-7
t GQX t GQV
Read Data
Write Data t DH t GQZ
/G
t SSR
/S
t HV t HZ Open Don't Care or Indeterminate NOTES: 1. If column address one equals column address two, then a read-modify-write cycle is performed.
/HIT
Open
2-52
Write-Per-Bit Cycle (/G=High)
t RE
t RP t CHR
/RE
t RSH t ACH
/CAL
t RAH t ASR
A0-7
t CAE t ASC t CAH Column t MSU t MH t CWL
A0-10
Row
W/R
t DMS t DMH Data t WRP t DS t DH t RRH t WP t RWL t WCH
DQ0-7
Mask
/WE
t WHR t MSU
/F
t SSR t MH t SHR
/S
t HV t HZ Open Don't Care or Indeterminate NOTES: 1. Data mask bit high (1) enables bit write; data mask bit low (0) inhibits bit write. 2. Write-per-bit cycle valid only for DM2213.
/HIT
Open
2-53
/F Refresh Cycle
/RE
t RE t MSU t MH t RP
/F
Don't Care or Indeterminate NOTES: 1. During /F refresh cycles, the status of W/R, /WE, A0-10, /CAL, /S, and /G is a don't care. 2. /RE inactive cache reads may be performed in parallel with /F refresh cycles.
/RE-Only Refresh
/RE
t ASR t RAH
t RE
tC t RP
A0-10
Row t NRS t NRH
/CAL, /WE, /G
t MSU
W/R, /F
t MH t SSR t SHR
/S
t HV t HZ Open Don't Care or Indeterminate NOTES: 1. All binary combinations of A0-9 must be refreshed every 64ms interval. A10 does not have to be cycled, but must remain valid during row address setup and hold times. 2. /RE refresh is write cycle with no /CAL active cycle.
/HIT
Open
2-54
Mechanical Data 44 Pin 300 Mil Plastic TSOP Package
0.741 (18.81) MAX. 0.0315 (0.80) TYP. Inches (mm)
0.040 (1.02) TYP.
0.040 (1.02) TYP.
0.040 (1.02) TYP.
0.044 (1.13) MAX.
7 TYP. 0.308 (7.82) 0.292 (7.42) 0.039 (1.00) 0.023 (0.60) 0.024 (0.60) 0.016 (0.40)
0.004 (0.10) 0.000 (0.00)
0.016 (0.40) 0.008 (0.20)
0.039 (1.00) TYP. 0.010 (0.24) 0.004 (0.09)
0.371 (9.42) 0.355 (9.02)
Part Numbering System
DM2203T - 12 I
Temperature Range No Designator = 0 to 70C (Commercial) I = -40 to 85C (Industrial) Access Time from Cache in Nanoseconds 12ns 15ns Packaging System T = 300 Mil, Plastic TSOP - II I/O Width i.e., Power to Which 2 is Raised for I/O Width (x8) Special Features Field 0 = No Write Per Bit 1= Write Per Bit Capacity in Bits i.e., Power to Which 2 is Raised for Total Capacity Dynamic Memory
The information contained herein is subject to change without notice. Enhanced Memory Systems Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in an Enhanced product, nor does it convey or imply any license under patent or other rights.
2-55

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